The present invention relates to semiconductor testing devices of LSI or the like, and more particularly to a test pattern generator wherein a large number of test patterns to be used in testing of a micro processor or the like are favorably generated at high speed.
In general, in testing of a logic LSI of a micro processor or the like, test patterns are previously stored in a memory of the testing device and then read at high speed, and thereby the test patterns are generated.
Since micro processors with high speed and high function have been developed in recent years, a large number of test patterns must be generated at very high speed in the testing thereof. In order to read the test patterns at high speed using a memory of low speed and large capacity, an interleave operation is known as the most effective means. As a test pattern generator using this means, for example, a device disclosed in Japanese patent application laid-open No. 128646/1979 is known. In testing of a logic LSI or the like, not only the test patterns are read in sequence, but also a function of reading one test pattern repeatedly and a function of branching the reading sequence are required. In the above-mentioned example of the prior art, in order to obtain these functions, a low-speed large-capacity memory is operated in an interleave manner and the output is stored in a high-speed small-capacity memory, and the repeated reading or the branch reading is performed. In this arrangement, however, since branching beyond the capacity of the high-speed memory is impossible, the test patterns cannot be read in an entirely arbitrary sequence.